1. Field of the Invention
The present invention relates to semiconductor device and, more particularly, to a structure of semiconductor chips for mounting a plurality of semiconductor chips onto a single package.
2. Description of the Prior Art
Normally, semiconductor device are used with a single semiconductor chip mounted on a single package. However, in order to increase the degree of integration, there are some cases in which a plurality of semiconductor chips are mounted within a single package.
Described below is a case in which a semiconductor chip 2, a semiconductor chip 4, and a semiconductor chip 6, as shown in FIG. 1, are mounted onto a single package. The chips 2, 4, and 6 are assumed to be as illustrated in the figure in their volume ratio. In each case, it is also assumed that a substrate 8 has an element portion 10 formed on its surface.
First, a bonding pad 2B is formed on an element formation surface of the chip 2 (FIG. 2A). The element formation surface of the chip 2 and the rear surface of the chip 4 on which a bonding pad 4B has been formed are bonded together with a nonconductive adhesive 15 such as epoxy resin (FIG. 2B). Similarly, the element formation surface of the chip 4 and the rear surface of the chip 6 on which a bonding pad 6B has been formed are bonded together with the adhesive 15 (FIG. 2C).
A semiconductor chip joint 14 thus constructed is then mounted onto a ceramic package 12 (see FIG. 3). Next, the bonding pad of the semiconductor chip joint 14 and respective conducting terminals on the outer end of the package 12 surrounding the chip are bonded together with a wire (normally aluminum wire). This can be performed by the normal wire bonding technique (not shown).
Thereafter, the package is covered with a cap and welding-sealed (not shown).
Also, among other methods by which a plurality of chips are mounted onto a single package, there is a method which employs new packages with the use of tabs (Nikkei Micro Device, Apr. 1991, p. 80).
This method is one in which two semiconductor chips 3 and 5 are sealed with their rear surfaces opposed to each other and then connected to lead frames 11 of a package 9 using tabs 7 (see FIG. 4).
Now the bonding process through which the chips and the lead frames are electrically connected is described below. The chips 3, 5 and the lead frames 11 are connected with the tabs 7 interposed therebetween. One end of a tab 7 is connected to the chip 3 using an Au bump 13 provided to the chip 3. Then the other end of the tab 7 is attached to one side of a lead frame 11. With the lead frame 11 turned over, the opposite side of the lead frame 11 and the chip 5 are connected through the Au bump 13 provided to the chip 5, using the tabs 7 in the same way as described above. Thereafter, the same process is repeatedly carried out so as to connect another lead frame to the chips 3 and 5.
Such a method as described above allows a plurality of semiconductor chips to be mounted onto a small-sized package.
Disadvantageously, however, such a high-density mounting method as described above has suffered from the following problems.
In the method as shown in FIG. 2, a chip to be piled on another is required to be smaller in area than that positioned below so as to allow a good use of the normal wire bonding technique. This requirement has caused limitations in terms of high-density mounting.
Meanwhile, the mounting method employing new packages with the use of tabs as shown in FIG. 4, although superior in terms of the degree of mounting integration, has had a problem that it cannot use the normal wire bonding technique, thus being complex in its bonding process.